1. Field
Example embodiments relate to a semiconductor device and a method of fabricating the same. Other example embodiments relate to a semiconductor device with a multi-level transistor structure and a method of fabricating the same.
2. Description of the Related Art
Usually in the field of semiconductor technology, semiconductor devices with multi-level transistor structures are studied in order to advance integration degrees of memory cells in a unit area. A semiconductor device with a multi-level transistor structure may be relatively tall, because multiple levels of insulation layers are stacked on a semiconductor substrate. Transistors may be formed in active region patterns on the multi-level insulation layers, which raises the integration density of transistors in a unit area.
Such a multi-level transistor structure is needed for semiconductor memory devices that require higher integration density. For instance, multi-level transistors are more suitable for cell array regions of flash memory devices or static RAMs, which include a single transistor or plural transistors in a unit cell, rather than dynamic RAMs employing a higher-level capacitor structure.
FIG. 1 is a diagram illustrating a conventional static RAM with a multi-level transistor structure. Referring to FIG. 1, the semiconductor memory device (e.g., a static RAM) may be configured to include a cell array region where memory cells are arranged, and a peripheral region where peripheral circuits are disposed. The cell array region may be required to have a higher integration degree for larger memory capacity, while the peripheral region needs to have higher performance peripheral circuits for improving operational performance of the semiconductor memory device.
As illustrated in FIG. 1, in the conventional static SRAM, the cell array region may be formed with multi-level transistor layers while the peripheral region may be formed with single-level transistors Tp on a substrate 10. The peripheral transistors Tp may be formed in active regions that are defined by field isolation films 14. Cell transistors T1, located at the bottom of the multi-level transistor layers, may be formed in the active regions defined by the field isolation films 14, similar to the peripheral transistors Tp. Cell transistors T2 and T3, located on upper layers over the cell transistor T1, may each be formed on semiconductor active patterns 18a and 22a and interposed among interlevel insulation films 16, 20, and 32. The transistors T1, T2, T3, and Tp may be connected to contact patterns 34 and interconnection layers 36 by circuit design
As illustrated in FIG. 1, the higher integration of the cell array region may be accomplished by adopting the multi-level transistor structure thereto. The transistors Tp may be formed in a structure of self-aligned silicidation for higher performance operation of the peripheral circuit. The silicidation structure may be constructed with self-aligned salicide layers (hereinafter, referred to as ‘salicide layers’) formed on source/drain regions and gate electrodes in the transistors. The silicidation structure may reduce sheet resistance of the source/drain regions and may provide a faster driving speed by forming ohmic layers among the source/drain regions, gate electrodes, and contact patterns.
As in the static RAM, the peripheral circuit transistors Tp may be formed at the same level with the lowest cell transistors T1. The peripheral circuit transistors may deteriorate while forming the multi-level cell transistors T2 and T3. For example, pollution due to diffusion of metal that forms the salicide layers 30 may deteriorate the peripheral circuit transistors Tp. The lowest cell transistors T1 may also increase resistance by silicide agglomeration. Accordingly, it may be more difficult to fabricate a higher-frequency and higher-performance semiconductor device because the peripheral circuits are degraded in operational performance.